Wafer-level testing and test during burn-in for integrated circuits
Saved in:
| Main Author: | |
|---|---|
| Corporate Author: | |
| Other Authors: | |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston :
Artech House,
2010.
|
| Series: | Artech House integrated microsystems series.
|
| Subjects: | |
| Online Access: | An electronic book accessible through the World Wide Web; click to view |
| Tags: |
No Tags, Be the first to tag this record!
|
Similar Items: Wafer-level testing and test during burn-in for integrated circuits
- Power-constrained testing of VLSI circuits
- Foundations for microstrip circuit design /
- An engineer's guide to automated testing of high-speed interfaces
- Compact models for integrated circuit design : conventional transistors and beyond /
- VLSI test principles and architectures design for testability /
- Understanding fabless IC technology