Cita APA (7th ed.)
Bahukudumbi, S., & Chakrabarty, K. (2010). Wafer-level testing and test during burn-in for integrated circuits. Artech House.
Cita Chicago (17th ed.)
Bahukudumbi, Sudarshan, i Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Boston: Artech House, 2010.
Cita MLA (9th ed.)
Bahukudumbi, Sudarshan, i Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Artech House, 2010.
Atenció: Aquestes cites poden no estar 100% correctes.