Bahukudumbi, S., & Chakrabarty, K. (2010). Wafer-level testing and test during burn-in for integrated circuits. Artech House.
Citação do estilo Chicago (17ª ed.)Bahukudumbi, Sudarshan, e Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Boston: Artech House, 2010.
Citação MLA (9ª ed.)Bahukudumbi, Sudarshan, e Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Artech House, 2010.
Nota: a formatação da citação pode não corresponder 100% ao definido pela respectiva norma.