Vertical 3D memory technologies /
I tiakina i:
| Kaituhi matua: | |
|---|---|
| Hōputu: | Tāhiko īPukapuka |
| Reo: | Ingarihi |
| I whakaputaina: |
Chichester, England :
Wiley,
2014.
|
| Ngā marau: | |
| Urunga tuihono: | An electronic book accessible through the World Wide Web; click to view |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
|
Ngā tūemi rite: Vertical 3D memory technologies /
- Power-constrained testing of VLSI circuits
- Handbook of 3D integration.
- Advanced interconnects for ULSI technology
- Mixed analog-digital VLSI devices and technology
- VLSI test principles and architectures design for testability /
- Verification by error modeling using testing techniques in hardware verification /