System-on-chip test architectures nanometer design for testability /
Furkejuvvon:
| Searvvušdahkki: | |
|---|---|
| Eará dahkkit: | , , |
| Materiálatiipa: | Elektrovnnalaš E-girji |
| Giella: | eaŋgalasgiella |
| Almmustuhtton: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
c2008.
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| Ráidu: | Morgan Kaufmann series in systems on silicon.
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| Fáttát: | |
| Liŋkkat: | An electronic book accessible through the World Wide Web; click to view |
| Fáddágilkorat: |
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Geahča maid: System-on-chip test architectures
- System-on-chip test architectures nanometer design for testability /
- VLSI test principles and architectures design for testability /
- VLSI test principles and architectures design for testability /
- Power-constrained testing of VLSI circuits
- Power-constrained testing of VLSI circuits
- Mixed analog-digital VLSI devices and technology