System-on-chip test architectures nanometer design for testability /
-д хадгалсан:
| Байгууллагын зохиогч: | |
|---|---|
| Бусад зохиолчид: | , , |
| Формат: | Цахим Цахим ном |
| Хэл сонгох: | англи |
| Хэвлэсэн: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
c2008.
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| Цуврал: | Morgan Kaufmann series in systems on silicon.
|
| Нөхцлүүд: | |
| Онлайн хандалт: | An electronic book accessible through the World Wide Web; click to view |
| Шошгууд: |
Шошго байхгүй, Энэхүү баримтыг шошголох эхний хүн болох!
|
Ижил төстэй зүйлс: System-on-chip test architectures
- System-on-chip test architectures nanometer design for testability /
- VLSI test principles and architectures design for testability /
- VLSI test principles and architectures design for testability /
- Power-constrained testing of VLSI circuits
- Power-constrained testing of VLSI circuits
- Mixed analog-digital VLSI devices and technology