Cita APA (7th ed.)
Radecka, K., & Zilic, Z. (2003). Verification by error modeling: Using testing techniques in hardware verification. Kluwer Academic Publishers.
Cita Chicago (17th ed.)
Radecka, Katarzyna, i Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Boston: Kluwer Academic Publishers, 2003.
Cita MLA (9th ed.)
Radecka, Katarzyna, i Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Kluwer Academic Publishers, 2003.
Atenció: Aquestes cites poden no estar 100% correctes.