Radecka, K., & Zilic, Z. (2003). Verification by error modeling: Using testing techniques in hardware verification. Kluwer Academic Publishers.
芝加哥风格引文Radecka, Katarzyna, 与 Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Boston: Kluwer Academic Publishers, 2003.
MLA引文Radecka, Katarzyna, 与 Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Kluwer Academic Publishers, 2003.
警告：这些引文格式不一定是100％准确.