APA引文

Radecka, K., & Zilic, Z. (2003). Verification by error modeling: Using testing techniques in hardware verification. Kluwer Academic Publishers.

Chicago Style (17th ed.) Citation

Radecka, Katarzyna, and Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Boston: Kluwer Academic Publishers, 2003.

MLA引文

Radecka, Katarzyna, and Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Kluwer Academic Publishers, 2003.