Verification by error modeling using testing techniques in hardware verification /

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Bibliographic Details
Main Author: Radecka, Katarzyna
Corporate Author: ebrary, Inc
Other Authors: Zilic, Zeljko
Format: Electronic eBook
Language:English
Published: Boston : Kluwer Academic Publishers, 2003.
Series:Frontiers in electronic testing ; 25.
Subjects:
Online Access:An electronic book accessible through the World Wide Web; click to view
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020 |z 1402076525 (alk. paper) 
035 |a (CaPaEBR)ebr10088540 
035 |a (OCoLC)228118912 
040 |a CaPaEBR  |c CaPaEBR 
050 1 4 |a TK7874.75  |b .R33 2003eb 
082 0 4 |a 621.39/5  |2 22 
100 1 |a Radecka, Katarzyna. 
245 1 0 |a Verification by error modeling  |h [electronic resource] :  |b using testing techniques in hardware verification /  |c written by Katarzyna Radecka, Zeljko Zilic. 
260 |a Boston :  |b Kluwer Academic Publishers,  |c 2003. 
300 |a xiv, 216 p. :  |b ill. 
490 1 |a Frontiers in electronic testing ;  |v 25 
504 |a Includes bibliographical references and index. 
533 |a Electronic reproduction.  |b Palo Alto, Calif. :  |c ebrary,  |d 2013.  |n Available via World Wide Web.  |n Access may be limited to ebrary affiliated libraries. 
650 0 |a Integrated circuits  |x Very large scale integration  |x Computer-aided design. 
650 0 |a Integrated circuits  |x Verification. 
650 0 |a Error analysis (Mathematics) 
655 7 |a Electronic books.  |2 local 
700 1 |a Zilic, Zeljko. 
710 2 |a ebrary, Inc. 
830 0 |a Frontiers in electronic testing ;  |v 25. 
856 4 0 |u http://site.ebrary.com/lib/daystar/Doc?id=10088540  |z An electronic book accessible through the World Wide Web; click to view 
908 |a 170314 
942 0 0 |c EB 
999 |c 69073  |d 69073