Citazione Stile APA (7a Edizione)
Radecka, K., & Zilic, Z. (2003). Verification by error modeling: Using testing techniques in hardware verification. Kluwer Academic Publishers.
Citazione stile Chigago Style (17a edizione)
Radecka, Katarzyna, e Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Boston: Kluwer Academic Publishers, 2003.
Citatione MLA (9a ed.)
Radecka, Katarzyna, e Zeljko Zilic. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Kluwer Academic Publishers, 2003.
Attenzione: Queste citazioni potrebbero non essere precise al 100%.