Verification techniques for system-level design
Tallennettuna:
| Päätekijä: | |
|---|---|
| Yhteisötekijä: | |
| Muut tekijät: | , |
| Aineistotyyppi: | Elektroninen E-kirja |
| Kieli: | englanti |
| Julkaistu: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
c2008.
|
| Sarja: | Morgan Kaufmann series in systems on silicon.
|
| Aiheet: | |
| Linkit: | An electronic book accessible through the World Wide Web; click to view |
| Tagit: |
Ei tageja, Lisää ensimmäinen tagi!
|
Samankaltaisia teoksia: Verification techniques for system-level design
- ESL design and verification a prescription for electronic system-level methodology /
- Networks on chips technology and tools /
- Comprehensive functional verification the complete industry cycle
- Designing SOCs with configured cores unleashing the Tensilica Xtensa and diamond cores /
- Verification of systems and circuits using LOTOS, Petri Nets, and CCS
- Network-on-chip : the next generation of system-on-chip integration /