Verification techniques for system-level design
में बचाया:
| मुख्य लेखक: | |
|---|---|
| निगमित लेखक: | |
| अन्य लेखक: | , |
| स्वरूप: | इलेक्ट्रोनिक ई-पुस्तक |
| भाषा: | अंग्रेज़ी |
| प्रकाशित: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
c2008.
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| श्रृंखला: | Morgan Kaufmann series in systems on silicon.
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| विषय: | |
| ऑनलाइन पहुंच: | An electronic book accessible through the World Wide Web; click to view |
| टैग: |
कोई टैग नहीं, इस रिकॉर्ड को टैग करने वाले पहले व्यक्ति बनें!
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समान संसाधन: Verification techniques for system-level design
- ESL design and verification a prescription for electronic system-level methodology /
- Networks on chips technology and tools /
- Designing SOCs with configured cores unleashing the Tensilica Xtensa and diamond cores /
- Comprehensive functional verification the complete industry cycle
- Verification of systems and circuits using LOTOS, Petri Nets, and CCS
- Network-on-chip : the next generation of system-on-chip integration /