System integration from transistor design to large scale integrated circuits /
I tiakina i:
| Kaituhi matua: | |
|---|---|
| Kaituhi rangatōpū: | |
| Hōputu: | Tāhiko īPukapuka |
| Reo: | Ingarihi |
| I whakaputaina: |
Chichester, West Sussex, England ; Hoboken, NJ :
John Wiley & Sons,
c2004.
|
| Ngā marau: | |
| Urunga tuihono: | An electronic book accessible through the World Wide Web; click to view |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
|
Ngā tūemi rite: System integration
- System integration from transistor design to large scale integrated circuits /
- Verification techniques for system-level design
- Verification techniques for system-level design
- System-on-chip test architectures nanometer design for testability /
- System-on-chip test architectures nanometer design for testability /
- Computer system design system-on-chip /