High-k gate dielectrics for CMOS technology
I tiakina i:
Kaituhi rangatōpū: | |
---|---|
Ētahi atu kaituhi: | , |
Hōputu: | Tāhiko īPukapuka |
Reo: | Ingarihi |
I whakaputaina: |
Weinheim :
Wiley-VCH,
2012.
|
Ngā marau: | |
Urunga tuihono: | An electronic book accessible through the World Wide Web; click to view |
Ngā Tūtohu: |
Tāpirihia he Tūtohu
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
|
Rārangi ihirangi:
- pt. 1. Scaling and challenging of Si-based CMOS
- pt. 2. High-k deposition and materials characterization
- pt. 3. Challenge in interface engineering and electrode
- pt. 4. Development in non-Si-based CMOS technology
- pt. 5. High-k Application in novel devices
- pt. 6. Challenge and directions.