APA ציטוט
Ferdjallah, M. (2011). Introduction to digital systems: Modeling, synthesis, and simulation using VHDL. Wiley.
Chicago Style (17th ed.) Citation
Ferdjallah, Mohammed. Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL. Hoboken, N.J.: Wiley, 2011.
ציטוט MLA
Ferdjallah, Mohammed. Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL. Wiley, 2011.
אזהרה: ציטוטים אלה לעיתים לא מדויקים ב 100%.