Ferdjallah, M. (2011). Introduction to digital systems: Modeling, synthesis, and simulation using VHDL. Wiley.
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Dyfyniad Arddull Chicago
Ferdjallah, Mohammed. Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL. Hoboken, N.J.: Wiley, 2011.
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Dyfyniad MLA
Ferdjallah, Mohammed. Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL. Wiley, 2011.
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Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.