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Verification by error modeling using testing techniques in hardware verification /

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書誌詳細
第一著者:	Radecka, Katarzyna
団体著者:	ebrary, Inc
その他の著者:	Zilic, Zeljko
フォーマット:	電子媒体 eBook
言語:	英語
出版事項:	Boston : Kluwer Academic Publishers, 2003.
シリーズ:	Frontiers in electronic testing ; 25.
主題:	Integrated circuits > Very large scale integration > Computer-aided design. Integrated circuits > Verification. Error analysis (Mathematics) Electronic books.
オンライン･アクセス:	An electronic book accessible through the World Wide Web; click to view
タグ:	タグ追加タグなし, このレコードへの初めてのタグを付けませんか!

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