Ngā hua rapu - Wang, Laung-Terng
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1
System-on-chip test architectures nanometer design for testability /
I whakaputaina 2008Ētahi atu kaituhi: “…Wang, Laung-Terng…”
An electronic book accessible through the World Wide Web; click to view
Tāhiko īPukapuka -
2
VLSI test principles and architectures design for testability /
I whakaputaina 2006Ētahi atu kaituhi: “…Wang, Laung-Terng…”
An electronic book accessible through the World Wide Web; click to view
Tāhiko īPukapuka