Cita APA (7a ed.)

ebrary, Inc, Wang, L., Stroud, C. E., & Touba, N. A. (2008). System-on-chip test architectures: Nanometer design for testability. Morgan Kaufmann Publishers.

Cita Chicago Style (17a ed.)

ebrary, Inc, Laung-Terng Wang, Charles E. Stroud, y Nur A. Touba. System-on-chip Test Architectures: Nanometer Design for Testability. Amsterdam ; Boston: Morgan Kaufmann Publishers, 2008.

Cita MLA (9a ed.)

ebrary, Inc, et al. System-on-chip Test Architectures: Nanometer Design for Testability. Morgan Kaufmann Publishers, 2008.