Tohutoro APA (7th ed.)
Bellido, M. J., Juan Chico, J., & Valencia, M. (2006). Logic-timing simulation and the degradation delay model. Imperial College Press.
Tohutoru Kātū Chicago (17th ed.)
Bellido, Manuel J., Jorge Juan Chico, me Manuel Valencia. Logic-timing Simulation and the Degradation Delay Model. London: Imperial College Press, 2006.
Tohutoro MLA (9th ed.)
Bellido, Manuel J., et al. Logic-timing Simulation and the Degradation Delay Model. Imperial College Press, 2006.
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