Bahukudumbi, S., & Chakrabarty, K. (2010). Wafer-level testing and test during burn-in for integrated circuits. Artech House.
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Lua i Stíl Chicago (17ú heag.)
Bahukudumbi, Sudarshan, agus Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Boston: Artech House, 2010.
Cóipeáladh chuig an ngearrthaisce go rathúil é
Níorbh fhéidir cóipeáil chuig an ngearrthaisce
Lua MLA (9ú heag.)
Bahukudumbi, Sudarshan, agus Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Artech House, 2010.
Cóipeáladh chuig an ngearrthaisce go rathúil é
Níorbh fhéidir cóipeáil chuig an ngearrthaisce
Rabhadh: Seans nach mbeach na luanna seo go hiomlán cruinn i ngach uile chás.