APA-viite (7. p.)
Bahukudumbi, S., & Chakrabarty, K. (2010). Wafer-level testing and test during burn-in for integrated circuits. Artech House.
Chicago-viite (17. p.)
Bahukudumbi, Sudarshan, ja Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Boston: Artech House, 2010.
MLA-viite (9. p.)
Bahukudumbi, Sudarshan, ja Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Artech House, 2010.
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