Cita APA
Bahukudumbi, S., & Chakrabarty, K. (2010). Wafer-level testing and test during burn-in for integrated circuits. Artech House.
Citación estilo Chicago
Bahukudumbi, Sudarshan, and Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Boston: Artech House, 2010.
Cita MLA
Bahukudumbi, Sudarshan, and Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Artech House, 2010.
Warning: These citations may not always be 100% accurate.